ü  Ph.D. in Electrical and Information Engineering, NCTU, June 1998.

ü  MS in Electrical Engineering, NCTU, June 1993.

ü  BS in Electronic Engineering, Fu-Jen Catholic Univ., June 1991.



From Oct. 1998 through Jan. 2002, Dr. Chang joined Computer and Communications Research Laboratories (CCL) at Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. During his early career time at CCL, he studied the high performance DSP architecture for real-time implementation of multimedia communication technology including H.263 video and G.723.1 low bitrate speech compression standards. Then, he worked on broadband cable modem transceiver technology, in which system simulations and architecture design are both involved. He also conducted two projects in advanced cable transceiver technology before leaving CCL.

In Feb. 2003, Dr. Chang joined the faculty of department of communication engineering at National Central University (NCU), Taoyuang, Taiwan. He keeps the pursuit of feasible algorithms, architecture, and implementation issues that meet industrial needs in wireless communications, especially in the fields of beyond 3G technologies. His recent research interests include transceiver architecture design, wireless OFDM technology, applications of multirate and adaptive signal processing, and FPGA rapid prototyping design on SoC platforms.


Past Technical Experience before the Career at NCU

Ø   2002/1~2002/12

At CCL/ITRI as a project leader in the Advanced Project Group for the "OFDM/CDMA Technology Research for Advanced Cable Modem Transceiver" project (class A with the highest budget support at CCL in the year).

-    The CableLabs DOCSIS 2.0 S-CDMA upstream transceiver standard

-    A proprietary OFDM/CDMA upstream architecture compatible to S-CDMA was studied

-    International collaborations with GATECH ECE Prof. N. Jayant and B. Bing in Broadband Institute and USC EE Prof. C.C. Jay Kuo in Multimedia Research Lab.

Ø   2001/4~2001/9

At CCL/ITRI as a project leader in the Advanced Project Group for the "High Speed DDFS Design" project (listed in first 8 projects out of whole ITRI's proposals in the year).

- A new DDFS architecture was developed and proposed.

Ø   1999/8~2001/12

At CCL/ITRI as a staff engineer in Broadband Cable Modem Transceiver Technology Project.

-    The CableLabs DOCSIS 1.0/1.1 cable modem

-    Study and teaching of cable transceiver system-level architect

-    Simulation and architecture design of some downstream modules, upstream system-level design, and downstream test-bed motherboard (AFE circuits)

Ø   1999/2~2000/1

At EE/FJU as an adjunct assistant professor.

- Teaching two courses: HDTV and Multirate Signal Processing

Ø   1998/10~1999/7

At CCL/ITRI as a staff engineer in Multimedia Communication Technology Project.

-    Study of DSP architecture, multimedia compression technology, and the real-time implementation technology

-    Design of DSP interfaces including DMA, Interrupter, and bus arbiter circuits

Ø   1998/3~1998/7

At CCL/ITRI for internship.

-    Study of high performance DSP architecture and implementation for the video phone DSP core

-    Study of H.263 video communication and G.723.1 low bitrate speech compression standards